I copy/paste here the article by Mike McGlinchy in Electronic Design because in that website the images are not showing properly.
pedalSHIELD is compatible with the arrangement described by M. McGlinchy by placing the jumper1:
By splitting the input signal into positive and negative portions and digitizing separately, this circuit allows a microcontroller’s unipolar ADC to handle bipolar signals and double its input range without compromising resolution.
Many microcontrollers (MCUs) incorporate onboard analog-to-digital converters (ADCs), usually with many multiplexed input channels. However, these ADCs are typically unipolar, able to handle only signals that are between the positive and negative reference voltages (+VREF to – VREF) with –VREF usually 0 V. To accommodate negative voltages, then, these ADCs need some form of signal conditioning.
The typical approach uses an op-amp dc level shifter that raises the signal by one half of +VREF so the entire analog signal excursion lies within the positive domain where the ADC can handle it. But there are two drawbacks to this approach. One is that shifting the signal cuts the positive headroom in half. Another drawback is the need for additional math firmware to remove the signal shift, which can reduce, perhaps significantly, the overall signal conversion rate.
This alternative approach breaks the incoming signal into its positive and negative components and digitizes them independently. It utilizes two of the microcontroller’s ADC channels along with a 4.096-V external voltage reference diode, two Schottky diodes, and both halves of a dual op amp.
Considering that the ADC likes a low impedance signal source (typically 10 kΩ, but a lower value is preferable for faster throughput), op amps are usually needed in a design to buffer a high impedance signal or sensor into a low impedance. Therefore, the dual op amp used here cannot really be considered an “extra” part.
The design example uses a midrange microcontroller, the PIC16F876 (U3), shown with only the pin connections pertaining to this technique (Fig. 1). The two halves of the op amp form a voltage follower with gain +1 (U1A) attached to the signal input followed by an inverter with gain –1 (U1B). The output of U1A attaches to analog input AN0 (U3, pin 2) through current-limiting resistor R1. Similarly, U1B attaches to AN1 through R4.
When VIN is positive—say, +4.00 V—U1A will present +4.00 V to AN0. Meanwhile, U1B will have –4.00 V on its output but the low-voltage-drop Schottky diode clips the negative voltage seen at AN1 (U3, pin 3) to about –0.24 V. Similarly, if VIN is –4.00 V, U1B will present +4.00 V to AN1 while D1 clips the –4.00 V from U1A to about –0.24 V at AN0.
Clipping the outputs in this way prevents a signal more negative than –0.30 V from appearing at either ADC input. Too negative a voltage at one input could cause current injection that would alter the other ADC channel’s results. The sample waveforms show a symmetrical 8-V p-p sine wave at VIN with the corresponding signals seen at the two ADC input channels (Fig. 2). The ADC will read any value equal to or below 0 V as zero.
The firmware to read the input signal must first select ADC channel 0 (AN0) and wait for the acquisition time of 40 µs or so, then trigger the ADC conversion. If the reading is not zero, then VIN is a positive voltage. Because VREF is 4.096 V, or 4 × 1024, the ADC reading is not the actual voltage but the number of 4-mV steps in the signal. If you need an exact voltage rather than a relative value, the firmware must multiply by four before storing the reading in RAM. (Two 8-bit locations will be needed because this is a 10-bit converter.)
If the reading for AN0 is zero, the firmware must select ADC channel 1 (AN1) and wait another 40 µs before performing a second conversion. If this result is not zero (for example, it’s 1.50 V), then VIN is negative (–1.50 V) and the firmware should convert the reading to a negative number before storing. If both AN0 and AN1 read as zero, then VIN = 0 V.
The circuit shown can digitize signals from +4.092 V to –4.092 V (8.184 V p-p) and can handle 10 V p-p if +VREF is set to +5 V (although converting the reading to the actual voltage becomes more complicated). The approach, then, doubles the ADC’s normal span while maintaining the same resolution.
Op amps with rail-to-rail inputs and outputs as well as low input-offset voltages will work best in this design. If speed is an issue, you can use faster op amps and a microcontroller with faster ADCs, playing the usual speed, accuracy, and power-consumption tradeoffs.
I included this jumper in the design because it is easy and provides extra features at zero cost. I have tried this configuration and works but there is crossover distortion which actually sounds like a subtle overdrive. In the future I will investigate more possibilities of this arrange.