delay_conv Table Question

Hi guys, new here, but not to building pedals. I'm looking at the delay_conv table and just trying to make sure I understand. It shows that delay times from 0 to 150 ms all have the same PWM duty cycle, right? If so, how does that jive with the circuit analysis that says we should be able to get down to 60 ms? I'm just trying to understand this, as I would like to condense the table down to save on SRAM usage, as I have some other code I'm combining this with that has several of its own global variables. Thanks!

After digging through some things on my own, there are a couple of things I have found that I figured I would put here.

1. To save on SRAM, there are two things that can be done. First, using data type uint8_t for the table cuts the amount of memory needed in half, saving a whopping 652 bytes. Additionally, since the table never changes, it can be put into PROGMEM, so it is stored in flash and uses zero SRAM. I am using both, just because I don't want to clog up my flash by using more bytes than necessary for the data.

2. It does appear that the same duty cycle is being used for the first 150 ms. This, along with the 52 identical values at the end for longer delay times, are limitations with an 8 bit timer. I have been planning to use the ATTiny84, which actually has a 16 bit timer, so resolution will be tons better. I am going to try to create a delay_conv table for 16 bit PWM resolution. Here's hoping I can automate it somehow...

3. One thing I had to convince myself of is that the higher duty cycle really does result in more current being sinked. I didn't doubt Ray, but I simulated it and did some thought experiments and it is true.